1. Field of the Invention
Example embodiments of the present invention relate to recovery circuits (e.g., clock and/or data recovery circuits) and methods for the same.
2. Description of the Conventional Art
Serial transmission of digital data between remote devices may, for example, reduce costs associated with wiring and/or suppress noise (e.g., cross-talk noise). For example, serial data transmission may allow an optical fiber, a coaxial cable or a twisted-pair cable to carry a serial stream of data bits at a higher speed than, for example, a parallel data transmission.
In conventional asynchronous communication, communication systems data may transmit data without a separate clock signal. If a separate clock signal is not used at a receiver side of communication systems, a clock recovery circuit (CRC) may be used to extract clock information from incoming data signals. Once clock information is extracted, the recovered clock may be used to re-time and regenerate the original data.
FIG. 1 is a block diagram illustrating a conventional clock recovery circuit using a phase locked loop (PLL). In the conventional clock recovery circuit (of FIG. 1), a multiplexer 120 may receive an input reference frequency clock 110 and serial data 100. The reference frequency clock 110 may be produced by a crystal oscillator, and may be a lower, or relatively lower, frequency clock.
The reference frequency clock 110 provided to the multiplexer 120 may be output as a higher frequency clock, for example, after passing through a feedback loop formed by a frequency phase detector 130, a loop filter 140, a voltage-controlled oscillator (VCO) 150, and a frequency divider 160.
For example, if the required frequency is about 2.00 GHz, 2.00 GHz of clock may be generated using a crystal oscillator having an oscillating frequency of 25 MHz and a frequency divider 160 having a division ratio of 80.
When the oscillated clock reaches about 2.00 GHz, serial input data 100, instead of the reference frequency clock 110, may be input to the phase locked loop (PLL) through the multiplexer 120, and a clock 180 synchronized to the serial input data 100, may be output. The clock 180, along with the serial input data 100, may be applied to a flip-flop 170 and a re-synchronized clock data 190 may be output.
A phase locked loop (PLL) may provide clock data synchronized to the higher-rate serial input data 100 in a reduced amount of time, for example, when the serial input data 100 contains jitter. Performance of the clock recovery circuit may depend on the performance of a phase locked loop (PLL), which may have a larger amount of power dissipation, larger chip area, design difficulty and/or noise.
Phase interpolation may be used to generate a clock having phase ranges between the phases of two input clocks, which have phases different from each other. For example, a clock having a phase in the range of 0-90 degrees may be generated using a clock having 0 degree phase and another clock having 90 degree phase.
A phase interpolator may be categorized into a digital phase interpolator and an analog phase interpolator. The digital phase interpolator may include multiple-staged delay element serially coupled each other. Each stage of the delay elements may have a delay different from another, and each delay element may output a different phase. The digital phase interpolator may obtain interpolated phases through a multiplexer that multiplexes the different phases output from each stage of the delay elements. Alternatively, the interpolated phases may be obtained by blending the different phases output from each stage of the delay elements.
FIG. 2 is a block diagram illustrating another conventional clock recovery circuit employing an analog phase interpolator.
Referring to FIG. 2, a phase detector 210 may generate a phase difference signal based on a phase comparison between serial input data 205 and an output clock 280. When a phase of the serial input data 205 leads a phase of the output clock 280, the phase detector 210 may generate a PDup having a high logic level and a PDdn having a low logic level. If a phase of the output clock 280 leads a phase of the serial input data 205, the phase detector 210 may generate a PDup having a low logic level and a PDdn having a high logic level. The PDup and PDdn signals output from the phase detector 210 may be input to a quadrant controller 220, and the quadrant controller 220 may determine a phase location of a phase of the output clock 280.
In this example, the first quadrant may have a phase range of 0-90 degrees, the second quadrant may have a phase range of 90-180 degrees, the third quadrant may have the phase range of 180-270 degrees and the fourth quadrant may have a phase range of 270-360 degrees. The quadrant controller 220 may map the PDup and PDdn signals to input signals Aup, Adn, Bup and Bdn of an amplitude controller 230.
The amplitude controller 230 may map the input signals Aup, Adn, Bup and Bdn to input signals Iup, Idn, Qup and Qdn of charge pump circuits 240 and 250. The amplitude controller 230 may control Iup, Idn, Qup and Qdn such that voltage control signals VA, VB, which may be provided to a mixer 260 and used for performing a phase interpolation, may be maintained within a desired amplitude range. For example, the voltage control signals VA, VB may be less than the desired maximum magnitude Vmax and may be greater than the desired minimum magnitude Vmin of the amplitude controller 230.
Referring again to FIG. 2, the mixer 260 may receive (e.g., selectively receive) I, Q, IB and QB clocks having a phase of 0 degrees, 90 degrees, 180 degrees and 270 degrees, respectively, according to the phase location of the output clock 280. The mixer 280 may perform a phase interpolation of the output clock 280 by applying weight values to the voltage control signals VA, VB to the received clocks I, Q, IB and/or QB. The phase-interpolated output clock 280 may be fed back to the phase detector 210.
FIG. 3 is a phase diagram illustrating a conventional relationship between voltage control signals VA, VB and a phase of a current output clock.
Referring to FIG. 3, the quadrant controller 220 may receive the voltage control signals Vref, VA, and VB to determine a phase location of the output clock 280. For example, the quadrant controller 220 may compare the voltage control signals VA and VB with the reference voltage signal Vref to determine the phase quadrant location of a phase of the output clock 280. The quadrant controller 220 may map the PDup and PDdn signals to Aup, Adn, Bup and Bdn of the amplitude controller 230 based on the phase location of the output clock 280.
When the first voltage control signal VA is greater than the reference voltage signal Vref, a phase of the output clock 280 may be located in either the first or fourth quadrant. In this example, the PDup may be mapped to Bup, and the PDdn may be mapped to Bdn in order to apply a weight value to Q clock having a phase of 90 degrees and a QB clock having a phase of 270 degrees.
Alternatively, when the first voltage control signal VA is less than the reference voltage signal Vref, a phase of the output clock 280 may be located in either the second or third quadrant. In this example, the PDup signal may be mapped to the Bdn signal, and the PDdn signal may be mapped to the Bup signal. This may result in an increase in the second voltage control signal VB in order to map the phases of the output clock 280 to that of the serial input data 205.
In another example, when the second voltage control signal VB is greater than the reference voltage signal Vref, a phase of the output clock 280 may be located in either the first or second quadrant. In this example, the PDup may be mapped the to and signal, and the PDdn signal may be mapped to the Aup signal.
Alternatively, when the second voltage control signal VB is less than the reference voltage signal Vref, a phase of the output clock 280 may be located in either the third or fourth quadrant. In this example, the PDup signal may be mapped to the Aup signal, and the PDdn signal may be mapped to the Adn signal.
This may result in the decrease of the first voltage control signal VA in order to delay the output clock 280, for example, when the output clock 280 leads the serial input data 205.
The amplitude controller 230 may receive the voltage Vmax (e.g., a maximum Vmax) and the voltage Vmin (e.g., minimum Vmin) to determine whether the voltage control signals VA, VB may be maintained within a voltage range. When the first or second voltage control signal VA or VB is greater than the voltage Vmax, the up components of the in-phase and quadrature phase control signals Iup, Qup may be set to zero in order to suppress (e.g., prevent) the first or second voltage control signal VA or VB from exceeding the voltage Vmax. In this case, the down components of the in-phase and quadrature phase control signals Idn and Qdn may be set equal to the down components of the first and second control signals Adn and Bdn, respectively.
Alternatively, when the first or second voltage control signal VA or VB is less than the voltage Vmin, the up components of the in-phase and quadrature phase control signals Iup and Qup may be set equal to the up components of the first and second control signals Aup and Bup, respectively. In this case, the down components of the in-phase and quadrature phase control signals Idn and Qdn may be set to zero in order to suppress (e.g., prevent) the first or second voltage control signal VA or VB from decreasing less than the voltage Vmin.
The amplitude controller 230 may suppress (e.g., prevent) the first and second voltage control signals VA and VB from surpassing the range.
The charge pump circuit 240 may receive the in-phase control signals Iup, Idn and the charge pump circuit 250 may receive the quadrature phase control signals Qup, Qdn in order to increase or decrease the voltage control signals VA, VB based on Iup, Idn, Qup, and Qdn and may provide the voltage control signals VA, VB to the mixer 260.
The mixer 260 may perform phase interpolations on four kinds of clocks I, Q, IB, QB using the voltage control signals VA, VB to generate the phase-interpolated output clock 280.